1. Field
This disclosure is generally related to wireless communications, and more particularly, to techniques for noise reduction for frequency synthesizers, such as delta-sigma noise reduction for wideband fractional-N frequency synthesizers.
2. Background
Synthesizers, such as fractional-N frequency synthesizers, are an important block in integrated wireless chips for diverse applications, such as chips for wireless communication systems. The synthesizer block generates the band selection, or local oscillator (LO) frequency, that may be used as a carrier in a wireless communication system.
In some applications, faster band selection mechanisms are desired. Faster band selection mechanisms are generally related to the extension of synthesizer loop bandwidth. Increasing the loop bandwidth generally reduces the loop settling time, and also generally relaxes the voltage controlled oscillator (VCO) design constraints, such as phase noise and power.
A sigma-delta modulator (SDM) that may be used in the synthesizer has been one of the major limiting factors in increasing the loop bandwidth due to a natural high pass frequency response. The impact of the natural high pass frequency response noise is more pronounced when using larger loop bandwidths. Consequently, fractional spurs may appear in the final spectrum and phase noise performance may be degraded.
Advances in communication systems lead to a consistent need for synthesizers with better performance and smaller area requirements. The need for wide bandwidth and low reference frequencies results in sigma delta quantization noise and higher integrated phase noise.
Various techniques have been employed to reduce delta-sigma noise in frequency synthesizers. One technique, discussed by Pamarti, et al., in “A wideband 2.4-GHz sigma delta fractional-N PLL with 1-Mb/s in-loop modulation,” IEEE J. Solid-State Circuits, vol. 39, pp. 49-62, January, 2004, which is entirely incorporated herein, describes a direct cancellation method that uses the error information from the SDM with negative polarity. The error information is then re-quantized and applied through a digital-to-analog converter (DAC) to the output of a charge pump to cancel the SDM error fed by the modulator and divider. However, the inherent mismatch in the direct cancellation method between the accumulated error within the loop and the correction path may limit the correction of the SDM error.
Another technique, discussed by Meninger and Perrott, in “A 1-MHz bandwidth 3.6 GHz 0.18-um CMOS fractional-N synthesizer utilizing a hybrid PFD/DAC structure for reduced broadband phase noise,” IEEE J. Solid-State Circuits, vol. 41, pp. 966-980, April, 2006, which is entirely incorporated herein, describes combination phase frequency detector/digital-to-analog converter (PFD/DAC) techniques that use the charge balance basics and an offset PFD. A correction window with the width of the period of the synthesized output signal (TVCO) is created and a charge pump pull down current is varied as a function of the accumulated error within that window. Such combination PFD/DAC techniques may have implementation costs associated with changing the PFD to incorporate up to four high speed flip flops running with the VCO clock and may be limited to accumulator based frequency synthesizers Using higher-order sigma delta based frequency synthesizers may degrade the performance of combination PFD/DAC techniques though the techniques best cancel the error when used with a simple sigma delta modulator or an accumulator.
Frequency synthesizers would benefit from more efficient noise reduction technique, including techniques to reduce the delta-sigma noise. Frequency synthesizers would benefit from an increase in the bandwidth of the synthesizer without the penalty of the closed loop phase noise. Various techniques have been employed to decrease noise in frequency synthesizers. However, the previous attempts remain inadequate to optimize the operation of the frequency synthesizers. Therefore, there is need for improvement.